i have control of the cortex-M3 and PIO core within the RP1Is it possible the RP1 chip used for GPIO on the Pi 5 has enough (undocumented) programmable I/O capability that the bit banging could be done more efficiently?
currently, i'm able to read gpio 0-15 at a rate of about 6mhz, and copy that ~84mbit/sec stream to host ram
in theory, i could take the pico-probe PIO code, load it in, and get things working
more into at viewtopic.php?t=363644
also:
edit:You are free to hack around with the hardware, but for anyone else wanting to experiment with this, heed these warnings:
The RP1 firmware expects unfettered access to the entirety of shared SRAM, starting at 0x2000_0000. Arbitrary modification of any part of the memory region may cause side-effects up to and including loss of data and hardware damage.
There are no guarantees about the layout of the firmware binary in a running system. The code in this repo is brittle and will likely fail on newer versions of RP1 firmware.
and increasing the dma source burst size, raised the speed limit to 300mbit!
Statistics: Posted by cleverca22 — Fri Jan 26, 2024 8:16 am