About dummy byte, it was at RX side. So very first pair od data will be writing byte containing FIFO address (whatever it is here) and complementary read (at the same clock edges) will be 'empty' - pulls value or random data maybe if no pulls available. Next 8 clock cycles will get you a first byte of data from accelerometer. But I guess you are missing:
to start both channels at the same time. Some after thoughts. About TX I guess you might just send that one register address and RX numer of bytes to get FIFO data. Or TX the same byte (register address) every time (non incrementing TX DMA address). Ideally it might be good to chain DMA channels. TX with one byte of register address and after its finish, starting DMA RX with FIFO number of bytes, but now without that dummy byte, since that 'empty' byte was skipped.
Code:
dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));Statistics: Posted by MatSOBDev2 — Fri Aug 02, 2024 7:05 pm