I'm having a problem where the DMA seems to get hung up transferring data to and from SPI. At the time of the hang,
TX DMA, channel number 0: dma_channel_config.ctrl = 0x80001 = 0b00000000000010000000000000000001, which has these bits set:
19: bits 20:15 are TREQ_SEL, so 0b010000 or 0x10 select DREQ 16 as TREQ, which is DREQ_SPI0_TX
0: DMA Channel Enable
RX DMA, channel number 1: dma_channel_config.ctrl = 0x88821 = 0b00000001000010001000100000100001
24: BUSY
19, 15: TREQ_SEL, so 0b010001: DREQ 17: DREQ_SPI0_RX
11: bits 14:11 are CHAIN_TO: When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel). In this case, this channel is 1.
5: INCR_WRITE
0: DMA Channel Enable
I'm trying to transfer a single block of 512 bytes. For the RX channel:
TRANSFER_COUNT (dma_hw->ch[1].transfer_count): 1
TRANS_COUNT reload value (DBG_TCR) (dma_debug_hw->ch[1].dbg_tcr): 512
DREQ counter (dma_debug_hw->ch[1].dbg_ctdreq): 0
The SPI has:
SSPCR0: 0b00000000000000000000001000000111, which has these bits set:
9: bits 15:8 are Serial Clock Rate (SCR); so 0b00000010, or 2
2:0: bits 3:0 are Data Size Select (DSS); so 0111: 8-bit data
SSPCR1: 0b00000000000000000000000000000010
1: 1 SSE Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
None of SPI_SSPSR_BSY_BITS, SPI_SSPSR_RFF_BITS, SPI_SSPSR_RNE_BITS, SPI_SSPSR_TNF_BITS, or SPI_SSPSR_TFE_BITS are set in SR.
What could be stopping it from transferring that final byte?
TX DMA, channel number 0: dma_channel_config.ctrl = 0x80001 = 0b00000000000010000000000000000001, which has these bits set:
19: bits 20:15 are TREQ_SEL, so 0b010000 or 0x10 select DREQ 16 as TREQ, which is DREQ_SPI0_TX
0: DMA Channel Enable
RX DMA, channel number 1: dma_channel_config.ctrl = 0x88821 = 0b00000001000010001000100000100001
24: BUSY
19, 15: TREQ_SEL, so 0b010001: DREQ 17: DREQ_SPI0_RX
11: bits 14:11 are CHAIN_TO: When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel). In this case, this channel is 1.
5: INCR_WRITE
0: DMA Channel Enable
I'm trying to transfer a single block of 512 bytes. For the RX channel:
TRANSFER_COUNT (dma_hw->ch[1].transfer_count): 1
TRANS_COUNT reload value (DBG_TCR) (dma_debug_hw->ch[1].dbg_tcr): 512
DREQ counter (dma_debug_hw->ch[1].dbg_ctdreq): 0
The SPI has:
SSPCR0: 0b00000000000000000000001000000111, which has these bits set:
9: bits 15:8 are Serial Clock Rate (SCR); so 0b00000010, or 2
2:0: bits 3:0 are Data Size Select (DSS); so 0111: 8-bit data
SSPCR1: 0b00000000000000000000000000000010
1: 1 SSE Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
None of SPI_SSPSR_BSY_BITS, SPI_SSPSR_RFF_BITS, SPI_SSPSR_RNE_BITS, SPI_SSPSR_TNF_BITS, or SPI_SSPSR_TFE_BITS are set in SR.
What could be stopping it from transferring that final byte?
Statistics: Posted by carlk3 — Tue Aug 27, 2024 12:33 am