That pattern could wrongfully lock the sync, I agree, but that suppose bit 6 to be always 1, then bit 7 always 0 (I think NL space, and many other characters below ASCII 64 will break the pattern), because the receiver looks for the transition from 1->0, then recheck at the middle of the cycle if it's still 0. In this regard It's pretty similar to Amega USART (16 clocks/UART bit).
So it would not last long, and once locked on the right start bit, it should recover and keep it, IF not disrupted by something else.
I would try to use simple config:without the rest ... especially NOT disabling FIFO
So it would not last long, and once locked on the right start bit, it should recover and keep it, IF not disrupted by something else.
I would try to use simple config:
Code:
gpio_set_function(4, GPIO_FUNC_UART); gpio_set_function(5, GPIO_FUNC_UART); uart_init(uart1, 115200); Statistics: Posted by gmx — Sat Dec 14, 2024 11:23 pm