I'm posting this here, since I've found no better way to reach out to the lovely folks at raspberrypi. Suggestions and comments are welcome.
While writing some PIO programs recently I found myself, having to use 2 registers and 4 or more instructions just to reset a scratch register to a (>31) fixed value (for countdown timers), and wishing there was a more compact way to reset both X and Y registers to a pre-defined 32bit value within my PIO programs.
Could y'all please consider adding support for this use case into the next PIO hardware revisions? To illustrate my feature request, here's what I imagine these changes to the PIO ISA could look like:
1. One new pioasm directive:
.dword <value>
[*]Stores a raw 32-bit value as two 32-bit aligned words in the program. This directive is invalid outside of a program.
2. One new instruction:
LOAD
Encoding
Operation
Load a 32-bit word from instruction memory into Destination
Destination:
000: Reserved
001: Reserved
010: Reserved
011: Reserved
100: Reserved
101: X (scratch register X)
110: Y (scratch register Y)
111: Reserved
Address:
An absolute address within the PIO instruction memory. Address value must be 32-bit word aligned (last bit is 0).
Assembler Syntax
where:
<destination> One of the destinations specified above.
<address> A program label or value representing the instruction offset within the program (the
first instruction being offset 0). Because the PIO LOAD instruction uses absolute addresses in the PIO
instruction memory, LOADs need to be adjusted based on the program load offset at runtime.
While writing some PIO programs recently I found myself, having to use 2 registers and 4 or more instructions just to reset a scratch register to a (>31) fixed value (for countdown timers), and wishing there was a more compact way to reset both X and Y registers to a pre-defined 32bit value within my PIO programs.
Could y'all please consider adding support for this use case into the next PIO hardware revisions? To illustrate my feature request, here's what I imagine these changes to the PIO ISA could look like:
1. One new pioasm directive:
.dword <value>
[*]Stores a raw 32-bit value as two 32-bit aligned words in the program. This directive is invalid outside of a program.
2. One new instruction:
LOAD
Encoding
Code:
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 || LOAD | 1 | 1 | 1 | Delay/side-set | Destination | Address |Operation
Load a 32-bit word from instruction memory into Destination
Destination:
000: Reserved
001: Reserved
010: Reserved
011: Reserved
100: Reserved
101: X (scratch register X)
110: Y (scratch register Y)
111: Reserved
Address:
An absolute address within the PIO instruction memory. Address value must be 32-bit word aligned (last bit is 0).
Assembler Syntax
Code:
load <destination>, <address><destination> One of the destinations specified above.
<address> A program label or value representing the instruction offset within the program (the
first instruction being offset 0). Because the PIO LOAD instruction uses absolute addresses in the PIO
instruction memory, LOADs need to be adjusted based on the program load offset at runtime.
Statistics: Posted by steffenyount — Wed Dec 18, 2024 11:03 pm