Yes, but it happens that a FETCH to access the same stripe as a WRITE, then one or the other have to be stalled together with the whole pipeline. I read that MPUs can reorder memory access to avoid/reduce such conflicts (with other compromises). With M33 can do it manually by changing the alignment, order of instructions, just it's quite challenging to predict when actually it takes place in relation with the fetch.
Statistics: Posted by gmx — Mon Mar 10, 2025 4:49 pm