In this case yes - because both values (zero and the intended value) are legitimate values with reasonable behaviour, and in any event the specific scheme in use here only works if the PIO is idle at the time the pull threshold is updated. An atomic update doesn't help - it needs to be correctly timed relative to the PIO program shifting bits out of the OSR, and there's no reasonable way to do that apart from waiting until the FIFO is empty and the program stalled. If the program is stalled,, it doesn't matter that it executes a few (stalled) cycles with the zero (meaning 32) pull threshold.But is it safe to do a clear, then a set to an active hardware register (multi-bit fields) ?
Usually the first write is applied immediately with all the consequences of an inconsistent intermediate value,
like crashing the system (think about a clock divider, or whatever critical), or running the peripheral astray, immediately.
Obviously there could be other register fields that you want to write in other programs where the zero intermediate value would cause trouble (like the clock divider example you mention) and in that case an atomic update (using XOR) would be helpful. Again you could just do read-modify-write with ordinary register accesses and that would be atomic with respect to the PIO hardware, but using the XOR mechanism makes it atomic with respect to other contexts (cores, IRQ handlers) that might want to update other fields in the same register.
Statistics: Posted by arg001 — Wed Apr 09, 2025 8:13 pm