Mine is still in the same state it was - works really well (on RP2040) but not yet reworked for release. If you have an urgent need, we could discuss ways of making it available sooner.
It should work equally well on RP2350.
Note that this is using just an ethernet PHY plus the RP2xxx PIO. Other people have mostly been using W5500 ethernet MAC+PHY<->SPI chips, which are more expensive and have lower max throughput and some other minor limitations, but are simpler to use. (as it happens, I already had W5500 experience from various things pre-dating RP2040).
One possible snag with my approach given your previous comments about what you use RP2350 for is clocking: for an ethernet PHY you fundamentally need a 50MHz (or possibly 25MHz if using MII rather than RMII) clock, so the RP2350 clock needs to be a multiple of this. To achieve it on RP2040 without overclocking, I down-clock to 100MHz, On RP2350, the nominal 150MHz should be usable. Or various overclock possibilities exist. But if you are running yours at a multiple of 12.288MHz then it's not going to work.
It should work equally well on RP2350.
Note that this is using just an ethernet PHY plus the RP2xxx PIO. Other people have mostly been using W5500 ethernet MAC+PHY<->SPI chips, which are more expensive and have lower max throughput and some other minor limitations, but are simpler to use. (as it happens, I already had W5500 experience from various things pre-dating RP2040).
One possible snag with my approach given your previous comments about what you use RP2350 for is clocking: for an ethernet PHY you fundamentally need a 50MHz (or possibly 25MHz if using MII rather than RMII) clock, so the RP2350 clock needs to be a multiple of this. To achieve it on RP2040 without overclocking, I down-clock to 100MHz, On RP2350, the nominal 150MHz should be usable. Or various overclock possibilities exist. But if you are running yours at a multiple of 12.288MHz then it's not going to work.
Statistics: Posted by arg001 — Tue Aug 05, 2025 9:13 pm