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Interfacing (DSI, CSI, I2C, etc.) • SN65DSI84 REFCLK and Flicker

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Hi,

I've got a custom board using a CM4 outputting DSI1 to a SN65DSI84 that drives a 10.1" 1280x800 LVDS display. I'm running bookworm with Linux 6.12.34. Thanks to the many posts by aBUGSworstnightmare, I've been able to piece together a working device tree and everything works (in large part due to the tip of using 3 lanes instead of 4).

Code:

/* * vc4-kms-dsi-ti-sn65dsi83-overlay.dts *//dts-v1/;/plugin/;/ {    compatible = "brcm,bcm2835";fragment@0 {target-path = "/";__overlay__ {sn65_power: regulator-sn65-enable {compatible = "regulator-fixed";regulator-name = "sn65-enable";gpio = <&pca9536 1 0>;enable-active-high;regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;};refclk_25m: refclk25 {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <25000000>;};panel: panel {compatible = "panel-lvds";//backlight = <&panel_backlight>;/* Physical dimensions of active area *//* Approx physical size for 10.1" 1280x800 */width-mm = <217>;height-mm = <136>;data-mapping = "vesa-24";/* 1280x800@60 (DCLK ~72.4 MHz) */panel-timing {clock-frequency   = <72400000>;hactive           = <1280>;hfront-porch      = <64>;hsync-len         = <32>;hback-porch       = <64>;vactive           = <800>;vfront-porch      = <5>;vsync-len         = <5>;vback-porch       = <28>;hsync-active      = <0>;vsync-active      = <0>;de-active         = <1>;pixelclk-active   = <0>;};port {panel_in_lvds: endpoint {remote-endpoint = <&bridge_out>;};};};};};fragment@1 {target = <&i2c1>;__overlay__ {#gpio-cells = <2>;#address-cells = <1>;#size-cells = <0>;status = "okay";pca9536: gpio-expander@41 {compatible = "nxp,pca9536";reg = <0x41>;gpio-controller;#gpio-cells = <2>;status = "okay";};lp8864@2b {compatible = "ti,lp8864";reg = <0x2b>;enable-gpios = <&pca9536 0 0>;status = "okay";panel_backlight: backlight {function = "backlight";max-brightness = <255>;default-state = "on";};};bridge@2c {//compatible = "ti,sn65dsi84";compatible = "ti,sn65dsi83";reg = <0x2c>;clocks = <&refclk_25m>;clock-names = "refclk";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;bridge_in: endpoint {remote-endpoint = <&dsi_out_port>;// 3-lane DSI is fine heredata-lanes = <0 1 2>;//data-lanes = <0 1 2 3>;};};port@2 {reg = <2>;bridge_out: endpoint {remote-endpoint = <&panel_in_lvds>;};};};};};};fragment@2 {target = <&dsi1>;__overlay__ {#address-cells = <1>;#size-cells = <0>;status = "okay";port {dsi_out_port: endpoint {remote-endpoint = <&bridge_in>;// 3l-lane DSI is fine here//data-lanes = <0 1 2 3>;data-lanes = <0 1 2>;};};};};};
I have an external oscillator (25MHz) wired into REFCLK and I tried enabling it in the above overlay but the SN65DSI84 isn't using it (confirmed by temporarily disabling it). The REFCLK does work, I confirmed by setting I2C registers on the SN65DSI84 and turning on the test pattern. Looking at the source code for the SN65DSI84 https://github.com/raspberrypi/linux/bl ... n65dsi83.c, I don't see anything obvious that would be setting the necessary registers. Does anyone have any experience using REFCLK? How is it defined in the overlay? Given that there is a known issue using the DSI as the source of the clock (CM5 and with higher resolutions), I'd rather avoid any future complications by using the REFCLK.

The acceptable range for REFCLK is pretty wide (25-154 MHz), any good rules of thumb for choosing? I know my display can handle an LVDS clock of 66.3-78.9MHz. Would it be good to set REFCLK to 75MHz (or some factor like 25MHz)?

I'm also seeing a flicker happen at a random interval (the animated gif is looping, doesn't happen nearly this frequently)
Image
Could that be related to the clock? It seems hardware related given that it doesn't happen at a consistent interval. If it helps, here's the timing for my LVDS display
lvds_timings.jpg
Thanks a lot.

Statistics: Posted by smithandrewc — Mon Oct 20, 2025 4:11 am



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