Also take in account that accessing system counters takes a few more cycles for each access because they are located on APB bus.
Not every instruction take just one cycle, a little less predictable with Cortex-M33 (pipelining, not necessarily external stalls), this is ARM stuff.
Better start the counter in free running, and take time snapshots at start and stop.
Can also use inline assembly for more predictable order.
If you want to count more precisely, use Systick, DWT CYCCNT (cycle counter), or RISC-V platform timer (SIO), and always check the disassembly.The APB bridge provides an interface between the high-speed main AHB5 interconnect and the lower-bandwidth
peripherals. Unlike the AHB5 fabric, which offers zero-wait-state accesses everywhere, APB accesses take a minimum
of three cycles for a read, and four cycles for a write.
Not every instruction take just one cycle, a little less predictable with Cortex-M33 (pipelining, not necessarily external stalls), this is ARM stuff.
Better start the counter in free running, and take time snapshots at start and stop.
Can also use inline assembly for more predictable order.
Statistics: Posted by gmx — Tue Nov 04, 2025 1:02 am