This was always going to be inherent in the architecture, so the idea was to offload as much bitbash as possible on to RP1 (hence PIO-over-mailbox). However there's a few deficiences in RP1 - namely the DMAC isn't great at fulfilling either latency or bandwidth requirements, there's no true multicore hardware support for the M3s to operate as a SMP cluster, and PIO only operates at the bus clock frequency (200MHz).Though not a product, I would like to see a thread on solutions to deal with the PCIe latency seen on Pi 5 and CM5 GPIO.The 1.2/2.4 usec latency on the PCIe interconnect to the RP1 was very nearly a killer, since I need to do a lot of small read/write transfers (think accessing a "classic" 8-bit data bus), although I've worked out a way to do that which is still a bit slow, but acceptably so.
Statistics: Posted by jdb — Thu Nov 20, 2025 8:59 am