It's not a fix, it's an optimisation.
The 2712 SoC has a small amount of on-chip SRAM - I can't remember the figure but for the sake of this explanation let's say 128KB (not MB!). The external memory on the board (1-16GB) can't be used until the DRAM controller has been initialised, and that takes several seconds. Most functions of the EEPROM bootloader are unusable until DRAM is available. Similarly, many functions of the Pi 5 are unusable until the RP1 firmware has been loaded, another task which takes a while but isn't very CPU intensive.
The change you are asking about overlaps the initialisation of the DRAM controller with the loading of the firmware for RP1, reducing the total boot time by a small amount.
The 2712 SoC has a small amount of on-chip SRAM - I can't remember the figure but for the sake of this explanation let's say 128KB (not MB!). The external memory on the board (1-16GB) can't be used until the DRAM controller has been initialised, and that takes several seconds. Most functions of the EEPROM bootloader are unusable until DRAM is available. Similarly, many functions of the Pi 5 are unusable until the RP1 firmware has been loaded, another task which takes a while but isn't very CPU intensive.
The change you are asking about overlaps the initialisation of the DRAM controller with the loading of the firmware for RP1, reducing the total boot time by a small amount.
Statistics: Posted by PhilE — Mon Nov 24, 2025 9:35 am