That's a bit disappointing. Using SPI6 will have reduced your CPU load a little, but apparently not increased the throughput. You're never going to get 30Mb/s through a 30MHz SPI link because of additional register accesses and inter-block gaps, but it's possible that the fact that the CS/CE lines are driven by the kernel as regular GPIOs might be increasing the time between transfers, reducing your bandwidth. I'll have a look at what would be required to allow HW CS to be selected, but it might need a driver change.
Statistics: Posted by PhilE — Wed Nov 26, 2025 9:38 am