Yes, the R/X bits are unfortunately swapped. Standard RISC-V ordering is (MSB to LSB) XWR, Hazard on RP2350 implements RWX instead. This slipped because there were no compatible upstream tests exercising X != R when we taped out, and I made the same RWX <-> XWR transposition in the Hazard3 tests so failed to catch the mistake.
This is documented as RP2350-E6 in the datasheet:
Recommendation is to use these defines from hardware/regs/rvcsr.h:
If a future device uses a newer version of Hazard3 (with the correct order) then those defines will be updated so software that uses them will continue to work. If we end up revving RP2350 with a newer version of Hazard3, I'll re-implement the field transposition bug so that RP2350 maintains binary compatibility.
This is documented as RP2350-E6 in the datasheet:
Code:
Reference RP2350-E6Summary PMPCFGx RWX fields are transposedAffects RP2350 A2, RP2350 A3, RP2350 A4Description The Physical Memory Protection unit (PMP) defines read, write and execute permissions (RWX) forconfigurable ranges of physical memory. The RWX permissions for four regions are packed into each 32-bit PMPCFG register, PMPCFG0 through PMPCFG3.Per the RISC-V privileged ISA specification, the permission fields are ordered X, W, R from MSB to LSB.Hazard3 implements them in the order R, W, X. This means software using the correct bit order will haveits read permissions applied as execute, and vice versa. (See upstream commit 7d37029.)Code:
RVCSR_PMPCFG0_R0_R_BITSRVCSR_PMPCFG0_R0_W_BITSRVCSR_PMPCFG0_R0_X_BITSStatistics: Posted by LukeW — Thu Jul 23, 2026 9:37 am
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