Hello.
I want to output PDM vía hardware as fast as possible. ¿Is there any peripheral that let's output PDM instead of PWM? Short answer, no. Is it easy to implement in software? Yes, I can use a small core but i will never be as fast as a hardware peripheral. Check this (implemented using a WCH mcu)...
https://github.com/Saco-de-patatas/CH32X0035-PDM
Can the RP2040 do the same with the PIO? Unfortunately there is no 32 bits adder so the use of a main core is mandatory, and then it can't work at system clock speed (one output state/cycle).
But the RP2040 has the interpolator, and It has 2 adders and accumulators, one per lane. Two accumulators and a bit masking (for implementing modulus operation) is what is all necessary for the interpolated PDM described at the link above. Furthermore, the OVERF flags in the INTERP0_CTRL_LANE0 Register could be used as the PDM result (because the PDM is the bit outside the adding/modulus operation).
The procedure would be...
0) initialize everything to 0.
1) let a DMA channel transfer a premade 12 bits sample to Base 0, and pace the DMA for 2^12 cycles.
2) for each cycle, let acc0 accumulate Base 0, and let Acc1 accumulate the result of lane0. Then mask Acc1 at (2^24-1).
3) Somehow, let the OVERF1 bit be transfered to the PIO fifo (another DMA chanel at sysclock pacing?), then the PIO would output the PDM bitstream throught any GPIO. At the same time, the interpolator should advance one interpolator cycle.
Problem: The only manner of advancing the interpolator is by reading the POP register, although this doesn't show the output of interest but the internal state of the PDM algorythm. And also, i don't see a way of serialize the OVERF1 bit into any PIO fifo.
Any ideas? Thanks.
I want to output PDM vía hardware as fast as possible. ¿Is there any peripheral that let's output PDM instead of PWM? Short answer, no. Is it easy to implement in software? Yes, I can use a small core but i will never be as fast as a hardware peripheral. Check this (implemented using a WCH mcu)...
https://github.com/Saco-de-patatas/CH32X0035-PDM
Can the RP2040 do the same with the PIO? Unfortunately there is no 32 bits adder so the use of a main core is mandatory, and then it can't work at system clock speed (one output state/cycle).
But the RP2040 has the interpolator, and It has 2 adders and accumulators, one per lane. Two accumulators and a bit masking (for implementing modulus operation) is what is all necessary for the interpolated PDM described at the link above. Furthermore, the OVERF flags in the INTERP0_CTRL_LANE0 Register could be used as the PDM result (because the PDM is the bit outside the adding/modulus operation).
The procedure would be...
0) initialize everything to 0.
1) let a DMA channel transfer a premade 12 bits sample to Base 0, and pace the DMA for 2^12 cycles.
2) for each cycle, let acc0 accumulate Base 0, and let Acc1 accumulate the result of lane0. Then mask Acc1 at (2^24-1).
3) Somehow, let the OVERF1 bit be transfered to the PIO fifo (another DMA chanel at sysclock pacing?), then the PIO would output the PDM bitstream throught any GPIO. At the same time, the interpolator should advance one interpolator cycle.
Problem: The only manner of advancing the interpolator is by reading the POP register, although this doesn't show the output of interest but the internal state of the PDM algorythm. And also, i don't see a way of serialize the OVERF1 bit into any PIO fifo.
Any ideas? Thanks.
Statistics: Posted by Sacodepatatas — Wed Feb 05, 2025 9:54 am