Thank you for your response!
This should cause the Core1 initiated bus requests have higher priority than the DMA R/W or core0 initiated requests,
Doesn't it mean that only DMA and Core0 requests should experience bus contention? (Core1 has the IRQs)
I understand that A2 vs A4 has no relevance, but the what does? And why do I experience differences on the two chips, what else could cause that?
Nope, everything is in RAM, I forgot to mention that important piece of information, sorry..Are you using flash at all?
That is why I set the Core1 bus priority to high, DMA R/W and Core0 bus prio is lowQ1: in theory the DMA could use a significant amount of bandwidth to one of the RAM blocks and so cut CPU performance by 50% or so (depending on priority settings, instruction mix etc).
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Code:
*(uint32_t *)BUSCTRL_BASE = 1<<4;Doesn't it mean that only DMA and Core0 requests should experience bus contention? (Core1 has the IRQs)
XIP access is executed only on core0, where no interrupts are configured and only when the core0 is idle (for a while).A related point (not your problem, but while we're on the subject) is that accessing the flash through XIP addresses ...
I have just recently turned off the logging via USB (by not calling the stdio_init_all() function - it means no IRQs are exeucuted, right?), but no difference. Anyway, PIO and GPIO IRQs are set to have the highest (0x00) priority, so USB related timer interrupts should not interfere here. Unless they turn off the interrupts for a while...Q2: Very unlikely that A2 vs A4 has any relevance. Much more likely is that you now have the USB connected (even if not actually using it for anything) and so taking 1kHz interrupts. That's likely to perturb the flash cache, change nesting of interrupts etc.
I understand that A2 vs A4 has no relevance, but the what does? And why do I experience differences on the two chips, what else could cause that?
Statistics: Posted by dikdom — Thu Dec 11, 2025 1:06 pm